The present invention is directed to brightness control. More particularly, the invention provides brightness control systems and methods with wide dimming range and adjustable minimum brightness. Merely by way of example, the invention has been applied to controlling brightness of cold-cathode fluorescent lamps (CCFLs). But it would be recognized that the invention has a much broader range of applicability.
The brightness of cold-cathode fluorescent lamps (CCFLs) can be controlled by conventional burst dimming technology. For burst dimming, a DC voltage is often received by a control chip, which, in response, adjusts the duty cycle of a low-frequency signal within the chip. This low-frequency signal is used to control a gate driver, whose output is further processed to adjust the brightness of the CCFLs. Sometimes, one or more of these CCFLs have an open circuit, so the control chip may also include an open-loop-protection (OLP) component. The OLP component can turn off the output of the gate driver if the control chip determines the current that flows through one or more CCFLs falls below a predetermined threshold level. But if the brightness of a CCFL becomes too low, the control chip may mistakenly infer the CCFL has an open circuit. Hence, the control chip usually sets a fixed minimum brightness internally.
FIG. 1 is a simplified diagram showing a conventional system for controlling brightness of one or more CCFLs. The system 100 includes a control chip 102, a power stage 104, a transformer 106, a CCFL 108, resistors 109 and 114, and capacitors 107, 134 and 154. Additionally, the control chip 102 includes a voltage generator 110, a voltage selector 120, an oscillator 130, a burst generator 140, an error amplifier 150, a gate driver 160, a logic component 170, an open-loop detector 180, and a protection component 190. Moreover, the control chip 102 also includes terminals 112, 122, 132, 152, 162, and 166.
As shown in FIG. 1, through the terminal 112, the voltage generator 110 is coupled to the resistor 114. The oscillator 130 and the burst generator 140 are coupled to the capacitor 134 through the terminal 132. Additionally, the error amplifier 150 is coupled to the CCFL 108 and the resistor 109 through the terminal 152. Moreover, the error amplifier 150 and the gate driver 160 are coupled to the capacitor 154 through the terminal 166. Also, the gate driver 160 is coupled to the power stage 104 through the terminal 162.
As an example, the control chip 102 regulates the start-up, normal operation, and protection of the system 100. Specifically, the control chip 102 sends a drive signal 164 to the power stage 104. The power stage 104 also receives a system input voltage (VIN) and generates a transformer input voltage, which is received by the transformer 106. The transformer 106, together with the capacitor 107, supplies a lamp voltage to the CCFL 108. The CCFL 108 is coupled to the resistor 109, which converts the current that flows through the CCFL 108 into a sensing voltage 158. The sensing voltage 158 is then received by the error amplifier 150 through the terminal 152.
As shown in FIG. 1, the error amplifier 150 is a part of the control chip 102, which also includes at least the voltage selector 120. The voltage selector 120 receives a DRC voltage (VDRC) and a dimming voltage (VDIM). The DRC voltage is a predetermined voltage, and is generated by one or more components internal to the control chip 102. In contrast, the dimming voltage can be adjusted and is supplied through the terminal 122 from one or more components that are external to the control chip 102. The voltage selector 120 compares VDRC and VDIM, and uses the lower of the these two voltages as its output voltage Vburst.
Additionally, the oscillator 130 is a low frequency oscillator. The oscillator 130, together with the capacitor 134, generates a ramp signal 136. The ramp signal 136 is received by the burst generator 140, which also receives the voltage Vburst. The burst generator 140 compares the voltage Vburst and the ramp signal 136, and generates a burst signal 142 (e.g., a pulse-width-modulation burst signal). The burst signal 142 is received by the error amplifier 150. The error amplifier 150 processes the received burst signal 142 and the received sensing voltage 158, and outputs a CMP signal 156 with the capacitor 154. The CMP signal 156 is sent to the gate driver 160.
As shown in FIG. 1, the control chip 102 also includes the logic component 170, the open-loop detector 180, and the protection component 190. The logic component 170 outputs an ENA signal 172 to the open-loop detector 180. The open-loop detector 180 also receives the sensing voltage 158. If enabled by the ENA signal 172, the open-loop detector 180 processes the sensing voltage 158, determines whether the CCFL 108 has an open circuit, and sends an OLP signal 182 to the protection component 190. In response, the protection component 190 outputs a signal 192 to the gate driver 160.
The gate driver 160 then processes the received signals 156 and 192 and sends the drive signal 164 through the terminal 162 to the power stage 104. If the OLP signal 182 indicates that the CCFL 108 has been determined to have an open circuit, the drive signal 164 would remain at the logic low level. Additionally, if the open-loop detector 180 is not enabled by the ENA signal 172, the drive signal 164 is not affected by the signal 192. For example, the drive signal 164 is generated based on the CMP signal 156, not the signal 192, if the ENA signal 172 is at the logic low level. Furthermore, the control chip 102 also includes the voltage generator 110. The voltage generator 110 provides a reference voltage to the resistor 114 through the terminal 112.
FIG. 2 is a simplified diagram showing convention signal curves for the system 100 for controlling brightness of one or more CCFLs. Specifically, a curve 210 represents the ramp signal 136 as a function of time, and a curve 220 represents the dimming voltage as a function of time. Additionally, a curve 230 represents the burst signal 142 as a function of time, and a curve 240 represents the drive signal 164 as a function of time. Moreover, a curve 250 represents a function of lamp current as a function of time. The lamp current is the current that flows through the CCFL 108. Alternatively, the curve 250 represents a function of the sensing voltage 158 as a function of time.
FIG. 3 is a simplified conventional diagram showing duty cycle of the burst signal 142 as a function of the dimming voltage for the system 100 for controlling brightness of one or more CCFLs. As shown in FIG. 3, if the dimming voltage is smaller than a first threshold level (Vth1) but larger than or equal to zero, the duty cycle of the burst signal 142 remains at 100%.
If the dimming voltage is equal to or larger than the first threshold level (Vth1) but smaller than or equal to the DRC voltage, the duty cycle of the burst signal 142 decreases with the increasing VDIM, along a straight line 310. As discussed above, the DRC voltage is a predetermined voltage that is generated by one or more components internal to the control chip 102. As shown in FIG. 3, if the dimming voltage is equal to the DRC voltage, the duty cycle is equal to a minimum level (Dmin). Additionally, if the dimming voltage is larger than the DRC voltage, the duty cycle remains at the minimum level (Dmin).
Specifically, the DRC voltage is a constant that is larger than the first threshold level (Vth1) and smaller than a second threshold level (Vth2). As shown in FIG. 3, the second threshold level (Vth2) corresponds to the intersection between the horizontal axis for VDIM and the extension of the straight line 310. Correspondingly, the minimum level (Dmin) is a constant that is lower than 100% but higher than zero.
Also, as shown in FIG. 1, the brightness of the CCFL 109 increases with the duty cycle of the burst signal 142. If the duty cycle of the burst signal 142 is at 100%, the brightness of the CCFL 109 is at the maximum. If the duty cycle of the burst signal 142 is at the minimum level (Dmin), the brightness of the CCFL 109 is at the minimum.
In addition to the burst dimming technology as discussed above, the brightness of CCFLs can also be controlled by conventional analog dimming technology. For analog dimming, an external voltage is often received by a control chip, which, in response, converts the received external voltage into an internal DC voltage. For example, the internal DC voltage is used to adjust the lamp current that flows through the CCFLs. In another example, the lamp current is proportional to the internal DC voltage. Hence, the brightness of the CCFLs can be changed by adjusting the internal DC voltage, which is often controlled by the external voltage.
FIG. 4 is a simplified diagram showing another conventional system for controlling brightness of one or more CCFLs. The system 400 includes a control chip 402, a power stage 404, a transformer 406, a CCFL 408, resistors 409 and 414, and capacitors 407 and 454. Additionally, the control chip 402 includes a voltage generator 410, a voltage selector 420, a level shifter 430, an error amplifier 450, a gate driver 460, a logic component 470, an open-loop detector 480, and a protection component 490. Moreover, the control chip 102 also includes terminals 412, 422, 452, 462, and 466.
As shown in FIG. 4, through the terminal 412, the voltage generator 410 is coupled to the resistor 414. Additionally, the error amplifier 450 is coupled to the CCFL 408 and the resistor 409 through the terminal 452. Moreover, the error amplifier 450 and the gate driver 460 are coupled to the capacitor 454 through the terminal 466. Also, the gate driver 460 is coupled to the power stage 404 through the terminal 462.
As an example, the control chip 402 regulates the start-up, normal operation, and protection of the system 400. Specifically, the control chip 402 sends a drive signal 464 to the power stage 404. The power stage 404 also receives a system input voltage (VIN) and generates a transformer input voltage, which is received by the transformer 406. The transformer 406, together with the capacitor 407, supplies a lamp voltage to the CCFL 408. The CCFL 408 is coupled to the resistor 409, which converts the current that flows through the CCFL 408 into a sensing voltage 458. The sensing voltage 458 is then received by the error amplifier 450 through the terminal 452.
As shown in FIG. 4, the error amplifier 450 is a part of the control chip 402, which also includes at least the voltage selector 420 and the level shifter 430. The level shifter 430 receives a dimming voltage (VDIM) and converts the dimming voltage (VDIM) into a shifted voltage (Vsft). For example, the dimming voltage can be adjusted and is supplied through the terminal 422 from one or more components that are external to the control chip 402. In another example, the shifted voltage is inversely proportional to the dimming voltage.
The shifted voltage (Vsft) is outputted to the voltage selector 420, which also receives a DRC voltage (VDRC). The DRC voltage is a predetermined voltage, and is generated by one or more components internal to the control chip 402. The voltage selector 420 compares VDRC and Vsft, and uses the higher of the these two voltages as its output voltage 442 (Vref). The output voltage 442 is received by the error amplifier 450. The error amplifier 450 processes the received output voltage 442 and the received sensing voltage 458, and outputs a CMP signal 456 with the capacitor 454. The CMP signal 456 is sent to the gate driver 460.
As shown in FIG. 4, the control chip 402 also includes the logic component 470, the open-loop detector 480, and the protection component 490. The logic component 470 outputs an ENA signal 472 to the open-loop detector 480. The open-loop detector 480 also receives the sensing voltage 458. If enabled by the ENA signal 472, the open-loop detector 480 processes the sensing voltage 458, determines whether the CCFL 408 has an open circuit, and sends an OLP signal 482 to the protection component 490. In response, the protection component 490 outputs a signal 492 to the gate driver 460.
The gate driver 460 then processes the received signals 456 and 492 and sends the drive signal 464 through the terminal 462 to the power stage 404. If the OLP signal 482 indicates that the CCFL 408 has been determined to have an open circuit, the drive signal 464 would remain at the logic low level. Additionally, if the open-loop detector 180 is not enabled by the ENA signal 472, the drive signal 464 is not affected by the signal 492. For example, the drive signal 464 is generated based on the CMP signal 456, not the signal 492, if the ENA signal 472 is at the logic low level. Furthermore, the control chip 402 also includes the voltage generator 410. The voltage generator 410 provides a reference voltage to the resistor 414 through the terminal 412.
FIG. 5 is a simplified diagram showing convention signal curves for the system 400 for controlling brightness of one or more CCFLs. Specifically, a curve 510 represents the dimming voltage as a function of time. Additionally, a curve 520 represents the output voltage 442 as a function of time. Moreover, a curve 530 represents a function of lamp current as a function of time. The lamp current is the current that flows through the CCFL 408. Alternatively, the curve 530 represents a function of the sensing voltage 458 as a function of time.
FIG. 6 is a simplified conventional diagram showing the output voltage 442 of the voltage selector 420 as a function of the dimming voltage for the system 400 for controlling brightness of one or more CCFLs. As shown in FIG. 6, if the dimming voltage is smaller than a first threshold level (Vth1) but larger than or equal to zero, the output voltage 442 remains at a maximum voltage level (Vmax).
If the dimming voltage is equal to or larger than the first threshold level (Vth1) but smaller than or equal to the DRC voltage, the output voltage 442 decreases with the increasing VDIM, along a straight line 610. As discussed above, the DRC voltage is a predetermined voltage that is generated by one or more components internal to the control chip 402. As shown in FIG. 6, if the dimming voltage is equal to the DRC voltage, the output voltage 442 is equal to a minimum voltage level (Vmin). Additionally, if the dimming voltage is larger than the DRC voltage, the output voltage 442 remains at the minimum level (Vmin).
Specifically, the DRC voltage is a constant that is larger than the first threshold level (Vth1) and smaller than a second threshold level (Vth2). As shown in FIG. 6, the second threshold level (Vth2) corresponds to the intersection between the horizontal axis for VDIM and the extension of the straight line 610. Correspondingly, the minimum level (Vmin) is a constant that is lower than Vmax but higher than zero.
Also, as shown in FIG. 4, the brightness of the CCFL 409 increases with the output voltage 442. If the output voltage 442 is at Vmax, the brightness of the CCFL 409 is at the maximum. If the output voltage 442 is at Vmin the brightness of the CCFL 409 is at the minimum.
But the conventional burst dimming technology and the conventional analog dimming technology often do not provide a wide range of brightness for CCFLs. Hence it is highly desirable to improve the techniques for brightness control.